Manufacturers of integrated circuits (“ICs”) continually strive for smaller elements for a higher density, full IC design on a wafer. For example, demands for elements whose feature sizes are less than 20 nm now exist. Optical and process corrected mask patterns are often required to meet these demands for features with finer resolution. To achieve the required resolution, the generation of the mask patterns can include optimizations to overcome inherent limitations, such as optical diffraction errors and edge placement errors (“EPE”), which occur during the lithographic pattern transfer process. The optimization can uses computational lithography modeling and optical proximity correction (OPC) techniques.